library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.SYNCHMODCTR;

entity TESTBNCH is
end TESTBNCH;

architecture stimulus of TESTBNCH is
	component SYNCHMODCTR is
    	port (
			Clk: in std_logic;
      		Rst: in std_logic;
      		O: out std_logic_vector(2 downto 0)
    	);
	end component;
	signal O: std_logic_vector(2 downto 0);
	constant PERIOD: time := 50 ns;
	signal Clk: std_logic;
	signal Rst: std_logic;
	signal done: boolean := false;
	FOR DUT : SYNCHMODCTR USE ENTITY WORK.SYNCHMODCTR;
begin
    DUT: SYNCHMODCTR port map ( 
		Clk,
		Rst,
		O
	);

    CLOCK1: process
        variable clktmp: std_ulogic := '0';
    begin
        wait for PERIOD/2;
        clktmp := not clktmp;
        Clk <= clktmp;  -- Attach your clock here
        if done = true then
           wait;
        end if;
    end process CLOCK1;

    STIMULUS1: process
    begin
	
    	Rst <= '1';  -- Reset the system
        wait for PERIOD; -- Wait one clock cycle
		Rst <= '0'; -- de-assert reset
        wait for 900 ns;
        
        done <= true;    -- Turn off the clock
        wait;            -- Suspend simulation
    end process STIMULUS1;

end stimulus;