library ieee;
use ieee.std_logic_1164.all;
entity SYNCHMODCTR is
	port (
    	Clk: in std_logic;
      	Rst: in std_logic;
      	O: out std_logic_vector(2 downto 0)
	);
end SYNCHMODCTR;

architecture BEHAVIOR of SYNCHMODCTR is
	component JKFF 
		port (
       	 	Rst: in std_logic;
        	Clk: in std_logic;
        	J: in std_logic;
        	K: in std_logic;
        	Q: out std_logic;
			QB: out std_logic
		);
	end component;
	signal OBAR: std_logic_vector(2 downto 0);
	signal OTEMP: std_logic_vector(2 downto 0);
	signal d1_decode_logic, d2_decode_logic: std_logic;
begin
	d1_decode_logic <= OBAR(2) and OTEMP(0);
	d2_decode_logic <= (OTEMP(2) and OBAR(1) and OTEMP(0)) or (OBAR(2) and OTEMP(1) and OTEMP(0)); 
	D0: JKFF port map (Rst,Clk,'1','1',OTEMP(0),OBAR(0));
	D1: JKFF port map (Rst,Clk,d1_decode_logic,d1_decode_logic,OTEMP(1),OBAR(1));
	D2: JKFF port map (Rst,Clk,d2_decode_logic,d2_decode_logic,OTEMP(2),OBAR(2));
	O <= OTEMP;
end BEHAVIOR;