library ieee;
use ieee.std_logic_1164.all;
entity JKFF is
    port (
        Rst: in std_logic;
        Clk: in std_logic;
        J: in std_logic;
        K: in std_logic;
        Q: out std_logic;
		QB: out std_logic
       );

end JKFF;

architecture BEHAVIOR of JKFF is
	signal Qreg, QregB: std_logic;
begin
    P1: process(Rst, Clk )
   	begin
        if Rst = '1' then
        	Qreg <= '0';
			QregB <= not Qreg;
		elsif Clk = '1' and Clk'event then
			Qreg <= (J and (not Qreg)) or ((not K) and Qreg) ; 
	     	QregB <= not ((J and (not Qreg)) or ((not K) and Qreg) );
		end if;
    end process P1;
	Q <= Qreg;
	QB <= QregB;
end BEHAVIOR;