Design & Implementation of a D Flip-Flop


D Flip-Flop

NOTE: Q* is defined as the next state of Q, while Q is the present state of Q.
 

INPUTS

OUTPUTS

PRESET

CLEAR

Clock

D

Q*

Q*’

L

H

X

X

H

L

H

L

X

X

L

H

L

L

X

X

H*

H*

H

H

Rising Edge of Clock

H

H

L

H

H

L

L

H

H

H

L

X

Previous Q

Previous Q’

 

 

Circuit Implementation