Design & Implementation of a Master/Slave J-K Flip-Flop
Objective
To design and build a S-R latch, and then use 2 of them to build a J-K M/S Flip-flop
Input/Outputs
For the SR Latch
Two one-bit inputs (S, R)
One one-bit enable line (ENABLE)
Two one-bit outputs (Q, Q’)
For the JK Flip-Flop
Two one-bit inputs (J, K)
One one-bit clock line (CLK)
Two one-bit outputs (Q, Q’)
Truth Tables
For the SR Latch
NOTE: Q* is defined as the next state of Q, while Q is the present state of Q.
INPUTS |
OUTPUTS |
|||||
ENABLE |
Q |
S |
R |
Q* |
Q*’ |
Notes |
0 |
X |
X |
X |
Previous Q |
Previous Q’ |
Circuit Not Enabled |
1 |
0 |
0 |
0 |
0 |
1 |
No Change |
1 |
0 |
0 |
1 |
0 |
1 |
Reset |
1 |
0 |
1 |
0 |
1 |
0 |
Set |
1 |
0 |
1 |
1 |
0 |
0 |
Undesired Condition |
1 |
1 |
0 |
0 |
1 |
0 |
No Change |
1 |
1 |
0 |
1 |
0 |
1 |
Reset |
1 |
1 |
1 |
0 |
1 |
0 |
Set |
1 |
1 |
1 |
1 |
0 |
0 |
Undesired Condition |
For the JK Flip-Flop
NOTE: Q* is defined as the next state of Q, while Q is the present state of Q. The
flip-flop we designed is negative-edge triggered. Thus, Q*/Q*’ will only change on
the falling edge of the clock cycle.
INPUTS |
OUTPUTS |
||||
Q |
J |
K |
Q* |
Q*’ |
Notes |
0 |
0 |
0 |
0 |
1 |
No Change |
0 |
0 |
1 |
0 |
1 |
Reset |
0 |
1 |
0 |
1 |
0 |
Set |
0 |
1 |
1 |
1 |
0 |
Toggle the output |
1 |
0 |
0 |
1 |
0 |
No Change |
1 |
0 |
1 |
0 |
1 |
Reset |
1 |
1 |
0 |
1 |
0 |
Set |
1 |
1 |
1 |
0 |
1 |
Toggle the output |
For the JK Master/Slave Flip-Flop
NOTE: Q* is defined as the next state of Q, while Q is the present state of Q.
INPUTS |
OUTPUTS |
|||
J |
K |
Q* |
Q*’ |
|
X |
X |
Previous Q |
Previous Q’ |
|
0 |
0 |
Previous Q |
Previous Q’ |
|
0 |
1 |
0 |
1 |
|
0 |
0 |
1 |
0 |
|
0 |
1 |
Previous Q’ |
Previous Q |
|
Karnaugh Maps
For the SR Latch
Q* |
|||||
Q |
S R |
||||
0 0 |
0 1 |
1 1 |
1 0 |
||
0 |
XX |
1 |
|||
1 |
1 |
XX |
1 |
||
XX= Undesired condition
Q* = S + Q . R’
For the JK Flip-Flop
Q* |
|||||
Q |
J K |
||||
0 0 |
0 1 |
1 1 |
1 0 |
||
0 |
1 |
1 |
|||
1 |
1 |
1 |
|||
Q* = Q . K’ + Q . J
Circuit Implementation
