library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.all;
entity TESTBNCH is
end TESTBNCH;
architecture stimulus of TESTBNCH is
	component JKFF is
    	port (
	  		Rst,Clk,J,K: in std_logic;
      		Q,QB: out std_logic
  		);
	end component;
	signal Clk: std_logic;
	signal Reset: std_logic;
	signal J, K: std_logic;
	signal Q,QB: std_logic;
	signal done: boolean := false;
	FOR DUT : JKFF USE ENTITY WORK.JKFF;

begin
    DUT: JKFF port map ( 
        	Reset,
        	Clk, 
			J,
           	K,
			Q,QB
          );

    CLOCK1: process
        variable clktmp: std_ulogic := '0';
    begin
        wait for 25 ns;
        clktmp := not clktmp;
        Clk <= clktmp;  
        if done = true then
           wait;
        end if;
    end process CLOCK1;
    STIMULUS1: process
    begin
		J <= '0'; K <= '0';
		Reset <='1';
		wait for 25 ns;
		Reset <= '0';
		wait for 25 ns;
		J <= '1';
		wait for 50ns;
		J <='0'; K <='1';
		wait for 50 ns;
		K <= '0';J <= '1';
		for m in 0 to 1 loop
    		for l in 0 to 1 loop
    			wait for 25 ns;
    			K <= not K;
			end loop;
    		--J <= not J;
    	end loop;
		J <= '1'; K<= '1';
       wait for 500 ns;
       done <= true;    
        wait;            
    end process STIMULUS1;
end stimulus;