library ieee;
use ieee.std_logic_1164.all;
entity DFF is
    port (
        Rst: in std_logic;
        Clk: in std_logic;
        D: in std_logic;
        Q: out std_logic;
		QB: out std_logic
       );
end DFF;

architecture BEHAVIOR of DFF is
	signal Qreg: std_logic;
	signal QregB: std_logic;
begin
    P1: process(Rst, Clk )
   	begin
        if Rst = '1' then
           Qreg <= '0';
			QregB <= '1';	
        elsif Clk = '1' and Clk'event then
			Qreg <= D; 
			QregB <= not D;
        end if;
    end process P1;
	Q <= Qreg;
	QB <= QregB;
end BEHAVIOR;