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-- Auto-generated module template: INVERTER
library ieee;
use ieee.std_logic_1164.all;

entity INVERTER is
    port (
        I: in std_logic;
        O: out std_logic
    );
end INVERTER;

architecture BEHAVIOR of INVERTER is
begin
	testit:  process is
	begin
		if    I = '0' then 
			O <= '1';
		elsif I = '1' then
		 	O <= '0';
		end if;
		wait on I;
	end process testit;

end BEHAVIOR;