library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.all;
entity TESTBNCH is end TESTBNCH;
architecture stimulus of TESTBNCH is
	component FIBONACCI is
    port (
        i3, i2, i1, i0: in std_logic;
        z: out std_logic
    );
	end component;
	signal i3, i2, i1, i0, z: std_logic;
	FOR DUT : FIBONACCI USE ENTITY WORK.FIBONACCI;
	
begin 
 DUT: FIBONACCI port map (i3, i2, i1, i0, z);
   	stimulus: process
   	begin
	i3 <= '0';
	i2 <= '0';
	i1 <= '0';
	i0 <= '0';
	for i in 0 to 1 loop
    	   	for j in 0 to 1 loop
				for k in 0 to 1 loop
					for l in 0 to 1 loop			
						wait for 25 ns;
						i0 <= not i0;				
					end loop;	
					i1 <= not i1;
				end loop;
				i2 <= not i2;
			end loop;
			i3 <= not i3;
		end loop;
	    wait;
   	end process;
end stimulus;