-- This is an 8-1 mux using 3 4to1MUX's
library ieee;
use ieee.std_logic_1164.all;
-- This is a fibonacci number detector using a 8:1 mux (which uses 3 4:1 mux's)

entity MUX8TO1_FIB is
    port (
        i3, i2, i1, i0: in std_logic;
        z: out std_logic
    );
end MUX8TO1_FIB;

architecture structure of MUX8TO1_FIB is
	component MUX8TO1
   	port (
        s_2, s_1, s_0: in std_logic;
        d_0, d_1, d_2, d_3,
			d_4,d_5,d_6,d_7: in std_logic;
        z_tot: out std_logic
    );
	end component;
	component INVERTER
    port (
        I: in std_logic;
        O: out std_logic
    );
	end component;
	signal i0_bar: std_logic;
begin
   	INVA: INVERTER port map (i0,i0_bar);
	MUX: MUX8TO1 port map (s_2=>i2,s_1=>i1,s_0=>i0,
							d_0=>i3,d_1=>i0_bar,d_2=>i0_bar,
							d_3=>i0_bar,d_4=>'0',d_5=>'1',
							d_6=>'0',d_7=>'0',z_tot=>z);

end structure;