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-- Auto-generated module template: DEMUX4TO1
library ieee;
use ieee.std_logic_1164.all;

entity DEMUX1TO4 is
    port (
        s1, s0: in std_logic;
        d: in std_logic;
        c0,c1,c2,c3: out std_logic
    );
end DEMUX1TO4;

architecture BEHAVIOR of DEMUX1TO4 is
begin
	testit:  process is
	begin
		if    s1 = '0' and s0 = '0' then 
			c0 <= d;
			c1 <= '0';
			c2 <= '0';
			c3 <= '0';
		elsif s1 = '0' and s0 = '1' then
			c0 <= '0';
		 	c1 <= d;
			c2 <= '0';
			c3 <= '0';
		elsif s1 = '1' and s0 = '0' then
			c0 <= '0';
			c1 <= '0';
			c2 <= d;
			c3 <= '0';
		else
			c0 <= '0';
			c1 <= '0';
			c2 <= '0';
			c3 <= d;
		end if;
		wait on d, s0, s1;
	end process testit;

end BEHAVIOR;