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-- Auto-generated module template: FULLADDER
library ieee;
use ieee.std_logic_1164.all;

entity BINTOGRAY is
    port (
        Bin3, Bin2, Bin1, Bin0: in std_logic;
        Gray3, Gray2, Gray1, Gray0: out std_logic
    );
end BINTOGRAY;

architecture BEHAVIOR of BINTOGRAY is
begin
	Gray3 <= Bin3;
	Gray2 <= Bin2 xor Bin3;
	Gray1 <= Bin1 xor Bin2;
	Gray0 <= Bin0 xor Bin1;
end BEHAVIOR;